1. Field of the Invention
The present invention is directed to the field of high speed computer buses. In particular, the present invention is directed to the field of current driven high speed computer buses.
2. Art Background
Computer buses provide the means for interconnecting a plurality of computer devices such that the devices may communicate with one another. The buses typically connect master devices such as microprocessors or peripheral controllers and slave devices such as memory components or bus transceivers. Typically the master and slave devices are located at a position along the bus and the bus is terminated at both ends of the transmission line of the bus. In a doubly terminated bus, both ends of the bus signal lines are connected to termination resistors of an impedance which corresponds to the impedance of the signal lines. Thus, when a signal is carried along the transmission line of the bus to the termination resistor, the resistor absorbs the signal eliminating signal reflections which may occur on the bus and cause erroneous signals.
When the bus is doubly terminated, each driver of a device on a bus must effectively drive two buses in parallel, one going to the left and one going to the right of the device's location on the bus. These signals propagate down the bus and the bus will then have been settled when both signals reach the termination resistors. The worst case signal settling time for this bus configuration is equal to the time-of-flight delay, t.sub.f, on the bus and which occurs when a driver on one end of the bus is transmitting to a receiver at the opposite end of the bus. The problem with this type of configuration is that the power dissipated by the device driving the bus is quite high since the impedance of the bus is relatively low.
Typically, buses are driven by voltage level signals. However, it has become advantageous to provide buses which are driven by current. One benefit to a current mode bus is a reduction of peak switching current. In a voltage mode device the output transistor of the driver must be sized to drive the maximum specified current under worst case operating conditions. Under nominal conditions with less than maximum load, the current transient when the output is switched, but before it reaches the rail, can be very large. The current mode driver on the other hand draws a known current regardless of load and operating conditions. In addition, impedance discontinuities occur when the driving device is characterized by a low output impedance when in a sending state. These discontinuities cause reflections which dictate extra bus settling time. Current mode drivers, however, are characterized by a high output impedance so that a signal propagating on the bus encounters no significant discontinuity in line impedance due to a driver in a sending state. Thus, reflections are avoided and the required bus settling time is decreased. An example of a current mode bus is disclosed in U.S. Pat. No. 4,481,625 issued Nov. 6, 1984, entitled "High Speed Data Bus System." A current mode bus is also disclosed in PCT international patent application number PCT/US91/02590 filed Apr. 16, 1991, published Oct. 31, 1991, and entitled Integrated Circuit I/O Using a High Performance Bus Interface assigned to the common assignee of the present invention.
Design requirements may dictate the use of MOS circuits. If the bus driver is comprised of CMOS integrated circuits, the signal voltage swing of external signals are typically rail to rail swings where the high level voltage is typically 3.3 to 5 volts and the low level voltage is zero volts. Such high voltage swings are not desirable in high speed transmission line buses because of the high level of induced noise and power dissipation. Other systems have sought to alleviate this problem by using various reduced voltage swings, such as GTL (Gunning Transistor Logic), signal levels (0.8 to 1.4 volts). GTL levels have in the past been optimized for voltage mode drivers and are too low in voltage to implement effective current mode drivers. An example of such a system is discussed U.S. Pat. No. 5,023,488, titled "Drivers and Receivers for Interfacing VLSI CMOS Circuits to Transmission Lines."